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700Mbps Sub-LVDS Rx PHY
  • 700Mbps Sub-LVDS Rx PHY 1번 상세이미지 썸네일

700Mbps Sub-LVDS Rx PHY


Key Featrues

  • 1.2V and 1.8V dual power supply

  • 2clock / 8data lane Rx(lane selectable by 4bit mode controls)

  • 700Mbps(350MHz DDR) for each lane / totally 5.6Gbps

  • 8/10/12/14/16 bit selectable parallel data output

  • Rail to rail receiver for multi level common mode application(0.9V and 0.2V)

  • 100ohm input termination resistors(internal poly resistor 80 ~ 125ohm)

  • Lane data and clock delay control(skew adjustment, manual setting)

  • Byte clock(parallel clock) interting function(1bit control per clock lane)