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High Speed Interface IPs

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Sub-LVDS Tx PHY
  • Sub-LVDS Tx PHY 1번 상세이미지 썸네일

Sub-LVDS Tx PHY

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Key Featrues




  • 1.2V and 1.8V Dual Power Supply



  • 700Mbps(350MHz DDR) data rate



  • Power down mode - Delay control for clock-data skew adjustment



  • 3-bit based mode selection(#of data channels)



  • 2 Channel output(1 Channel : 4 data driver, 1 Clock drier)



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