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High Speed Interface IPs

LeoLSI has been accumulating plentiful knowhow for Analog IP design including Converters, High Speed Interface, PLL, OSC and PMICs, through over 10 years IP design experience on various foundry sites. LeoLSI has the ability to accelerate the IP development ,integration for smaller size and lower power, which can specialize, optimize customers applications and requirements accordingly.

Data Converter(ADC / DAC) IPs

Our data converter includes general purpose ADCs, DACs and special function data converters designed for wide range of application.

High Speed Interface(HSI) IPs

LeoLSI has experienced HSI PHY design of MiPi, eDP, HDMI, etc. with specialized engineers who can collaborate from spec. targetting to mass production supports.

Clock Generator(PLL / OSC) IPs

Various PLL design experience not only general purpose but also high speed for specific applications and OSCs for use as watch-god timers and system clock generator for MCUs.

Other IPs

Power management IPs are developed including Power-On Reset generator (POR), Low Drop Out Voltage Regulator(LDO), and Programmable gain amplifiers. Also we have experienced special IP design based on customer requirement.

Various foundry vendor experience

LeoLSI has experienced various foundry sites by porting standard and customized Analog IPs to many customer products
Converter IPs
High Speed Interface IPs
PLL & OSC IPs
Other IPs
MiPi D-PHY V1.2
<a href='/product/ip.php?ptype=view&prdcode=1908160014&page=1&catcode=11110000'>MiPi D-PHY V1.2</a>
  • <a href='/product/ip.php?ptype=view&prdcode=1908160014&page=1&catcode=11110000'>MiPi D-PHY V1.2</a> 1번 상세이미지 썸네일

MiPi D-PHY V1.2

제품상세정보테이블

Key Featrues

  • Supprot MiPi D-PHY v1.2
  • Support Max. 4-lane MiPi D-PHY mode
  • Support both high speed mode and low power modes
  • 80Mbps to 1.5Gbps data rate per lane without skew calibration
  • uptp 2.5Gbps data rate per lane with skew calibration
  • 10Mbps per data lane in low power mode
  • Support internal loopback mode foer testability
제품상세정보테이블
HF-mini LVDS Tx
<a href='/product/ip.php?ptype=view&prdcode=1908160013&page=1&catcode=11110000'>HF-mini LVDS Tx</a>
  • <a href='/product/ip.php?ptype=view&prdcode=1908160013&page=1&catcode=11110000'>HF-mini LVDS Tx</a> 1번 상세이미지 썸네일

HF-mini LVDS Tx

제품상세정보테이블

Key Featrues

  • Analog 2.5V / 3.3V, 1.1V power supply
  • Digital 1.1V single power supply
  • Output frequency range : 90MHz ~ 300MHz
  • Individual power down mode : Channel power down & Data driver power down
  • 4 to 1 Serialize
  • Including PLL
  • 4-Channel output(1Channel : 5 Data driver, 1 Clock driver)
제품상세정보테이블
700Mbps Sub-LVDS Rx PHY
<a href='/product/ip.php?ptype=view&prdcode=1908160012&page=1&catcode=11110000'>700Mbps Sub-LVDS Rx PHY</a>
  • <a href='/product/ip.php?ptype=view&prdcode=1908160012&page=1&catcode=11110000'>700Mbps Sub-LVDS Rx PHY</a> 1번 상세이미지 썸네일

700Mbps Sub-LVDS Rx PHY

제품상세정보테이블

Key Featrues

  • 1.2V and 1.8V dual power supply
  • 2clock / 8data lane Rx(lane selectable by 4bit mode controls)
  • 700Mbps(350MHz DDR) for each lane / totally 5.6Gbps
  • 8/10/12/14/16 bit selectable parallel data output
  • Rail to rail receiver for multi level common mode application(0.9V and 0.2V)
  • 100ohm input termination resistors(internal poly resistor 80 ~ 125ohm)
  • Lane data and clock delay control(skew adjustment, manual setting)
  • Byte clock(parallel clock) interting function(1bit control per clock lane)
제품상세정보테이블
700Mbps Sub-LVDS Tx PHY
<a href='/product/ip.php?ptype=view&prdcode=1908160011&page=1&catcode=11110000'>700Mbps Sub-LVDS Tx PHY</a>
  • <a href='/product/ip.php?ptype=view&prdcode=1908160011&page=1&catcode=11110000'>700Mbps Sub-LVDS Tx PHY</a> 1번 상세이미지 썸네일

700Mbps Sub-LVDS Tx PHY

제품상세정보테이블

Key Featrues

  • 1.2V and 1.8V dual power supply
  • 700Mbps(350MHz DDR) data rate
  • Power down mode
  • Delay control for clock-data skew adjustment
  • 3 bit based mode selection(# of data channels)
  • 2 channel output(1 channel : 4data driver, 1 clock driver)
제품상세정보테이블
Sub-LVDS Tx PHY
<a href='/product/ip.php?ptype=view&prdcode=1908120002&page=1&catcode=11110000'>Sub-LVDS Tx PHY</a>
  • <a href='/product/ip.php?ptype=view&prdcode=1908120002&page=1&catcode=11110000'>Sub-LVDS Tx PHY</a> 1번 상세이미지 썸네일

Sub-LVDS Tx PHY

제품상세정보테이블

Key Featrues

  • 1.2V and 1.8V Dual Power Supply
  • 700Mbps(350MHz DDR) data rate
  • Power down mode - Delay control for clock-data skew adjustment
  • 3-bit based mode selection(#of data channels)
  • 2 Channel output(1 Channel : 4 data driver, 1 Clock drier)
제품상세정보테이블
12~85Mhz LVDS Rx
<a href='/product/ip.php?ptype=view&prdcode=1908120001&page=1&catcode=11110000'>12~85Mhz LVDS Rx</a>

12~85Mhz LVDS Rx

제품상세정보테이블

Key Featrues

  • 12 to 85MHz Shift clock support
  • Low Power consumption
  • ±1V Common-mode range(around +1.2V)
  • Up to 2.38Gbps throughput
  • Up to 297.53Mbytes/sec bandwidth
  • 345mV(typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Rising / Falling edge data strobe
제품상세정보테이블